Search - risc verilog

[Embeded-SCM Develop] freerisc8_11.zip

Description: 8位RISC　CPU的VERILOG编程　SOURCECODE
Platform: | Size: 275274 | Author: | Hits:

[Other resource] embedded_risc

Description: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Platform: | Size: 128616 | Author: 箫勇天 | Hits:

[Other resource] RiscCpu

Description: 用verilog编写的risc mcu -verilog prepared with the risc mcu
Platform: | Size: 9542 | Author: 谢迪 | Hits:

[Other resource] VCDwtHDLV

Description: < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘
Platform: | Size: 875012 | Author: wiyn | Hits:

[Other resource] RISC_Core.ZIP

Description: 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序
Platform: | Size: 340784 | Author: jinzhoulang | Hits:

[Other resource] 32-bit_RISC_IP_Core

Description: 32位RISC单片机verilog源码内包含说明文档经过他人测试通过
Platform: | Size: 34078 | Author: 栾日超 | Hits:

[OS Develop] minirisc.tar

Description: verilog code .descrip the risc cpu.download from opencores.org
Platform: | Size: 74434 | Author: 刘科麟 | Hits:

[Other resource] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 79444 | Author: 张念华 | Hits:

[Other resource] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44088 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19456 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。 PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
Platform: | Size: 3147776 | Author: vice | Hits:

[VHDL-FPGA-Verilog] RISC-Verification

Description: reduced instruction set of computer in verilog
Platform: | Size: 658432 | Author: Nisha | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
Platform: | Size: 3288064 | Author: | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
Platform: | Size: 4337664 | Author: 刘栋 | Hits:

[Other] risc-4-way-lru-processor-verilog

Description: A RISC processor written in verilog codes.
Platform: | Size: 95232 | Author: gnuhcyee | Hits:

[VHDL-FPGA-Verilog] minirisc-master

Description: Implementation of the MiniRisc CPU in Verilog!
Platform: | Size: 90112 | Author: loox_dg | Hits:

[VHDL-FPGA-Verilog] Chapter4

Description: MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
Platform: | Size: 24576 | Author: Tom1215 | Hits:

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[Embeded-SCM Develop] freerisc8_11.zip

[Other resource] embedded_risc

[Other resource] RiscCpu

[Other resource] VCDwtHDLV

[Other resource] RISC_Core.ZIP

[Other resource] 32-bit_RISC_IP_Core

[OS Develop] minirisc.tar

[Other resource] ethernet_verilog

[Other resource] risc_cpu

[VHDL-FPGA-Verilog] dll11254

[VHDL-FPGA-Verilog] RISC-CPU

[VHDL-FPGA-Verilog] RISC-Verification

[VHDL-FPGA-Verilog] RISC-CPU

[VHDL-FPGA-Verilog] RISC-CPU

[Other] risc-4-way-lru-processor-verilog

[VHDL-FPGA-Verilog] minirisc-master

[VHDL-FPGA-Verilog] Chapter4

[VHDL-FPGA-Verilog] Chapter8

[VHDL-FPGA-Verilog] RISC

[VHDL-FPGA-Verilog] RISC

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